1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having pads disposed at a periphery of the semiconductor integrated circuit chip and multilevel wiring means electrically connected to the pads.
2. Description of the Related Art
Recently, fine pattern technologies of semiconductor devices have been rapidly developed, and the integration density of the semiconductor integrated circuit device (hereinafter referred to as "an LSI") has increased. When the integration density of the LSI is raised, high function and multi-function LSIs are naturally manufactured as products.
However, the high function and multi-function LSIs require more electric means for connecting the exterior of the device to the interior of the device. In other words, the LSI necessitates a number of pads.
The arrangement of the pads in the conventional LSI will be considered.
FIG. 11 is a plan view showing the most general conventional LSI. In the drawing, reference numeral 100 denotes an LSI chip, and pads 101 to be electrically connected to external terminals of a lead frame are arranged in one row along four sides of the chip. I/O circuits 102 of the LSI 100 are also formed in one row inside the rows of the pads 101. FIG. 12 is an enlarged view of the vicinity of the pads of the LSI shown in FIG. 11. In FIG. 12, it is understood that the I/O circuits 102 and the pads 101 are disposed at a predetermined pitch and are connected through interconnection layers 104 with one another.
Further, a plan view in FIG. 13 shows an LSI which has been proposed in order to increase the number of pads 101 while suppressing its area. In FIG. 13, reference numerals correspond to those in FIG. 11. In other words, the pads 101 are zigzag arranged to suppress both an increase in the pads 101 and an increase in the area of the LSI due to the increase in the pads 101. FIG. 14 is an enlarged view showing the vicinity of pads 101 of the LSI illustrated in FIG. 13. However, it is not still improved to suppress the increase in the area of the LSI. FIG. 15 shows an LSI which has been proposed in order to further suppress the increase in the area, illustrating an enlarged view of the vicinity of the pads thereof. That is, in the LSI with the zigzag arranged pads shown in FIG. 15, the width of interconnection layers 104 passing among pads 101 is reduced to suppress the increase in the area. However, in such an LSI, the reliability of the interconnection layers 104 may be lowered because the width of each interconnection layer is reduced. That is, since the current density flowing through interconnection layers 104 is increased, an unwanted electromigration may occur.